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The Precourt Institute for Energy is now part of the Stanford Doerr School of Sustainability.

Energy-Efficient 3D Electronics by Layer Transfer of Fully Patterned Low-Dimensional Devices

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Precourt Pioneering Project

Awarded in the area of Energy Efficiency Computing to solve critical challenges in energy, climate, and integrated energy systems.
Award start date: January 1, 2022.


Computing systems today that use large off-chip memory can expend over 90% of their energy shuttling data back-and-forth. This project aims to tackle the energy associated with this through dense 3-dimensional integrated circuits (3D-ICs) with stacked memory and computing layers on a single chip. Monolithically integrated 3D-ICs have been estimated to offer over 50x lower energy consumption than conventional computing approaches. Depending on the application, 3D-ICs can save enormous amounts of energy in the IT realm, on a global scale, from the edge to the cloud. This project will use a multipronged approach to realize these structures. Materials will be rethought and architecture
design techniques that tolerate possible misalignment will be employed.

Project Goal

This project aims to use a novel approach for 3D-ICs built with misalignment-tolerant device layer transfers to lower the energy associated with data storage and memory use in the computing systems of today. The team will complete device fabrication before transfers to enable the parallel fabrication of all levels in the 3D-IC and provide a scalable approach for a multilevel 3D architecture. This approach will be less time consuming and less costly than the sequential patterning of devices on each layer. Ultimately the team will demonstrate several layers of stacked active devices (i.e., transistors), test their performance, and investigate proof-of-concept circuits such as vertically stacked inverters and logic circuits to demonstrate the flexibility of the approach.


The team will:

  • study the fabrication and transfer of completed device structures (i.e., transistors, memory, interconnects)
  • develop the process for vertical stacking with interlayer dielectrics (ILDs)
  • perform the transfer with an alignment accuracy of microns on a ~cm2 scale in a customized microscope setup dedicated for the transfer of low-D materials
  • translate constraints on overall layer alignment into circuit design rules, and analyze impact on system area, energy and delay


1. M. Malakoutian, A. Kasperovich, D. Rich, K. Woo, C. Perez, R. Soman, D. Saraswat, J.-k. Kim, M. Noshin, M. Chen, S. Vaziri, X. Bao, C.C. Shih, W.-Y. Woon, M. Asheghi, K.E. Goodson, S. Liao, S. Mitra and S. Chowdhury. 2023. “Cooling Future System-on-Chips with Diamond Inter-Tiers,” Cell Reports Physical Science. 

2. Q. Lin, C. Gilardi, S.-K. Su, Z. Zheng, E. Chen, P. Bandaru, A. Kummel, I. Radu, S. Mitra, G. Pitner and H.-S.P. Wong. 2023. “Band-to-band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube MOSFETs,” ACS Nano. 

3. A. Daus, L. Hoang, C. Gilardi, S. Wahid, J. Kwon, S. Qin, J.-S. Ko, M. Islam, A. Kumar, K.M. Neilson, K. C. Saraswat, S. Mitra, H.-S. Philip Wong and Eric Pop. 2023. “Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability,” IEEE Trans. Electron Devices. 

4. Ç. Köroğlu, E. Pop. 2023. "High Thermal Conductivity Insulators for Thermal Management in 3D Integrated Circuits," IEEE Electron Device Lett. 

5. R.K.A. Bennett, E. Pop. 2023. "How Do Quantum Effects Influence the Capacitance and Carrier Density of Monolayer MoS2 Transistors?" Nano Letters. 

6. W. Li, X. Gong, Z. Yu, L. Ma, W. Sun, S. Gao, Ç. Köroğlu, W. Wang, L. Liu, T. Li, H. Ning, D. Fan, Y. Xu, X. Tu, T. Xu, L. Sun, W. Wang, J. Lu, Z. Ni, J. Li, X. Duan, P. Wang, Y. Nie, H. Qiu, Y. Shi, E. Pop, J. Wang, X. Wang. 2023. "Approaching the Quantum Limit in Two-Dimensional Semiconductor Contacts," Nature 613, 274-279. 

7. Y. Kobayashi, C. Heide, A. C. Johnson, V. Tiwari, F. Liu, D. A. Reis, T. F. Heinz, and S. Ghimire. 2023. “Floquet engineering of strongly driven excitons in monolayer tungsten disulfide,” Nature Physics. 

Team Members

Eric Pop

Eric Pop
Professor of Electrical Engineering, and Materials Science & Engineering by courtesy Pop will lead the device fabrication, the device-layer-transfer, and thermal analysis.


Tony Heinz

Tony Heinz
Professor of Applied Physics & Photon Science, Associate Lab Director for Energy Sciences, SLAC. 
Heinz brings 2D and CNT characterization expertise, and contacts to ASML which are key to eventually combine our in-house layer transfer process with commercial wafer steppers, which should lead to ~10 nm alignment accuracy

Andrew Mannix
Andrew Mannix is an Assistant Professor of Materials Science & Engineering. Mannix will provide wafer-scale 2D materials growth, atomic-scale STM for defect characterization, and transfer expertise including a robotic transfer system.


Subhasish Mitra
Professor of Electrical Engineering and Computer Science
Mitra will provide CNT device fabrication, transfer, and the misalignment-tolerant approach for monolithic 3D-ICs to develop proof-of-concept vertically inter- connected circuits.