The Precourt Institute for Energy is part of the Stanford Doerr School of Sustainability.

3D MOSAIC: A Co-Design Approach Spanning Device and Integration Technologies, Architectures and Algorithms for Large Energy Benefits

Precourt Pioneering Project

Awarded in the area of Energy Efficiency Computing.
Award start date: January 1, 2022.

Background

Computation demands today far exceed the capabilities of existing systems. Large amounts of data are collected on “edge” devices, then transmitted and processed in the cloud, using many energy-hungry central processing units, GPUs, and TPUs that are connected to energy-hungry memories. To reduce the amount of energy used and improve overall energy efficiency, one approach would be to perform computation on the edge devices thereby reducing the transmission of data and processing by the cloud. However, there are several challenges with this. Edge systems are highly constrained, and traditional approaches to improving computing are stalling: computing systems are increasingly dominated by the time and energy shuttling data back-and-forth between the compute chip and the memory chip (memory wall); traditional (transistor) miniaturization will eventually stop in a decade (miniaturization wall); and many existing algorithms aren’t well-suited for hardware implementations, especially for highly-constrained edge systems. 

Project Goal

This project is an inter-disciplinary effort with team expertise across multiple domains including algorithms, VLSI architectures and circuits, nanotechnologies and nanosystems, integration technologies, and electronic design automation. The team plans to target computation at the edge and explore new architectures co-designed with applications. The goal is to achieve 3D MOSAIC (MOnolithic/Stacked/Assembled IC) that will achieve large energy and execution-time benefits.  Specific tasks are outlined below.

Tasks

The overall end-to-end concept, called 3D MOSAIC (MOnolithic/Stacked/Assembled IC), to achieve large energy and execution time benefits will be explored based on the following foundations:

  • New 3D chips for computation immersed in memory through dense 3D integration (e.g., monolithic 3D) of interleaved layers of logic and memory, and no off-chip memory (Mitra, Wang).

  • New multi-chip integration with sub-5μm scale connectivity between multiple 3D chips using high-resolution Continuous Liquid Interface Production (CLIP) technology (DeSimone, Mitra).

  • New architectures at multiple scales: (a) new chip-level accelerators that exploit dense on-chip hybrid memory technologies and 3D integration (Raina, Mitra), and (b) scaleup with growing problem sizes through new multi-chip Illusion (exploiting CLIP multi-chip integration) that orchestrates multiple 3D chips to create an illusion of a Dream1 Chip with near-Dream energy and throughput (Mitra, DeSimone).

  • New hardware-aware algorithms for AI, linear algebra, and related kernels to enable chip-level accelerators to meet underlying hardware constraints, especially for the edge (Pilanci, Mitra, Raina).

  • Fast and explainable framework for end-to-end joint co-exploration and co-optimization (i.e., codesign) of technologies, architectures, and algorithms (Mitra, Pilanci, Raina).

Publications

1. G. Cauwenberghs, J. Cong, X.S. Hu, S. Joshi, S. Mitra, W. Porod and H.-S.P. Wong. 2023. “Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities,” Proceedings of the IEEE. 

2. T. Ergen, M. Pilanci. 2023. “Path Regularization: A Convexity and Sparsity Inducing Regularization for Parallel ReLU Networks,” Neural Information Processing Systems (NeurIPS). 

3. R. Saha, V. Srivastava, M. Pilanci.2023. “Matrix Compression via Randomized Low Rank and Low Precision Factorization," Neural Information Processing Systems (NeurIPS). 

4. R. Dwaraknath, T. Ergen, M. Pilanci. 2023. “Fixing the NTK: From Neural Network Linearizations to Exact Convex Programs," Neural Information Processing Systems (NeurIPS). 

5. T. Ergen, M. Pilanci. 2023. “Path Regularization: A Convexity and Sparsity Inducing Regularization for Parallel ReLU Networks,” Neural Information Processing Systems (NeurIPS). 

6. Xue, F., Lin, S. J., Song, M., Hwang, W., Klewe, C., Lee, C. M., Turgut, E., Shafer, P., Vailionis, A., Huang, Y. L., Tsai, W., Bao, X., Wang, S. X. 2023. “Field-free spin-orbit torque switching assisted by in-plane unconventional spin torque in ultrathin [Pt/Co]N,” Nature Communications.

7. Hwang, W., Xue, F., Zhang, F., Song, M., Lee, C., Turgut, E., Chen, T. C., Bao, X., Tsai, W., Fan, D., Wang, S. X. 2023. “Energy Efficient Computing With High-Density, Field-Free STT-Assisted SOT-MRAM (SAS-MRAM),” IEEE Trans. Magnetics. 

Subhasish Mitra
Professor of Electrical Engineering and Computer Science. Subhasish will have responsibility for all aspects of the project, monitor the project, and ensure that the research goals are met. He will collaborate with the PIs on almost every aspect of 3D MOSAIC.

Joseph M. DeSimone

Joseph M. DeSimone
Professor of Chemical Engineering, School of Medicine, Graduate School of Business. Joe DeSimone will have responsibility for CLIP-based integration aspects of 3D MOSAIC. He will collaborate with PI Mitra on Illusion.

Mert Pilanci 
Professor of Electrical Engineering. Mert Pilanci will focus on hardware-aware algorithms and co-design. He will collaborate with PI Mitra and co-PI Raina. 

Priyanka Raina
Professor of Electrical Engineering. Priyanka will focus on 3D chip-level architectures and co-design. She will mostly collaborate with PI Mitra and co-PI Pilanci, and to some extent with co-PI Wang on Hybrid RAM (MRAM and RRAM).

Shan X. Wang
Professor of Electrical Engineering, and Material Science and Engineering. Shan Wang will mostly collaborate with PI Mitra on 3D chips with Hybrid RAM (MRAM and RRAM) and with co-PI Raina.