3D MOSAIC: A Co-Design Approach Spanning Device and Integration Technologies, Architectures and Algorithms for Large Energy Benefits
Precourt Pioneering Project
Awarded in the area of Energy Efficiency Computing to solve critical challenges in energy, climate, and integrated energy systems.
Award start date: January 1, 2022.
Computation demands today far exceed the capabilities of existing systems. Large amounts of data are collected on “edge” devices, then transmitted and processed in the cloud, using many energy-hungry central processing units, GPUs and TPUs that are connected to energy-hungry memories. To reduce the amount of energy used and improve overall energy efficiency, one approach would be to perform computation on the edge devices themselves thereby reducing transmission of data and processing by the cloud. However, there are several challenges with this. Edge systems are highly constrained, and traditional approaches traditional approaches to improving computing are stalling: computing systems are increasingly dominated by the time and energy shuttling data back- and-forth between the compute chip and the memory chip (memory wall); traditional (transistor) miniaturization will eventually stop in a decade (miniaturization wall); and many existing algorithms aren’t well-suited for hardware implementations especially for highly-constrained edge systems.
This project is an inter-disciplinary effort with team expertise across multiple domains including algorithms, VLSI architectures and circuits, nanotechnologies and nanosystems, integration technologies, electronic design automation. The team plans to target computation at the edge and explore new architectures co-designed with applications. The goal is to achieve 3D MOSAIC (MOnolithic/Stacked/Assembled IC) that will simultaneously achieve large energy and execution-time benefits. Specific tasks are outlined below.
The overall end-to-end concept, called 3D MOSAIC (MOnolithic/Stacked/Assembled IC), to achieve large energy and execution time benefits will be explored based on the following foundations:
- New 3D chips for computation immersed in memory through dense 3D integration (e.g., monolithic 3D) of interleaved layers of logic and memory, and no off-chip memory (Mitra, Wang).
- New multi-chip integration with sub-5μm scale connectivity between multiple 3D chips using high resolution Continuous Liquid Interface Production (CLIP) technology (DeSimone, Mitra).
- New architectures at multiple scales: (a) new chip-level accelerators that exploit dense on-chip hybrid memory technologies and 3D integration (Raina, Mitra), and (b) scaleup with growing problem sizes through new multi-chip Illusion (exploiting CLIP multi-chip integration) that orchestrates multiple 3D chips to create an illusion of a Dream1 Chip with near-Dream energy and throughput (Mitra, DeSimone).
- New hardware-aware algorithms for AI, linear algebra and related kernels that enable chip-level accelerators to meet underlying hardware constraints especially for the edge (Pilanci, Mitra, Raina).
- Fast and explainable framework for end-to-end joint co-exploration and co-optimization (i.e., codesign) of technologies, architectures, and algorithms (Mitra, Pilanci, Raina).
Professor of Electrical Engineering and Computer Science
Investigator will have responsibility for all aspects of the project, monitor the project, ensure that the research goals are met in a timely manner with scientific integrity, and work within the budgeted funds. He will collaborate with the PIs on almost every aspect of 3D MOSAIC
Joseph M. DeSimone
Professor of Chemical Engineering, School of Medicine, Graduate School of Business
He will have responsibility for CLIP-based integration aspects of 3D MOSAIC. He will collaborate with PI Mitra on Illusion.
Professor of Electrical Engineering
He will focus on hardware-aware algorithms and co-design. He will collaborate with PI Mitra and co-PI Raina.
Professor of Electrical Engineering
She will focus on 3D chip-level architectures and co-design. She will mostly collaborate with PI Mitra and co-PI Pilanci, and to some extent with co-PI Wang on Hybrid RAM (MRAM and RRAM).
Shan X. Wang
Professor of Electrical Engineering, and Material Science and Engineering
He will mostly collaborate with PI Mitra on 3D chips with Hybrid RAM (MRAM and RRAM) and with co-PI Raina.